Very Large Scale Integrated (VLSI) circuits are designed using a variety of Computer Aided Design (CAD) tools. The development of VLSI circuits with CAD tools is often referred to as Electronic Design Automation (EDA). A VLSI circuit can be characterized by a netlist. A netlist is a list of circuit components and interconnections between the circuit components. An EDA tool known as a static timing analyzer is used to verify that the circuit described in the netlist meets timing requirements.
A static timing analyzer accesses circuit timing performance by relying upon timing attributes, as specified in a library of timing models, for individual circuit components in the netlist. The library of timing models includes timing information for each circuit component in the netlist. The timing information includes such information as the input pin capacitance, input-to-output delay, and output drive strengths. Combining this library along with a design netlist, a static timing analyzer generates critical path timing information statically without knowledge of the design's logical functionality.
The timing estimates associated with a static timing analyzer are not as accurate as those provided by a circuit simulator. Circuit simulators such as SPICE or HSPICE can be considered dynamic timing analyzers, although they are used for more than timing analyses. Since a circuit simulator simulates the actual operation of a circuit at the transistor level, it is relatively time consuming to obtain results from a circuit simulator, compared to a static timing analyzer that does not simulate the operation of the component, but uses static timing information for the component.
It would be highly desirable to provide a design tool that verifies the timing information supplied by a static timing analyzer. Preferably, such a tool would utilize a circuit simulator, but not be hampered by the computational expense typically associated with the operation of a circuit simulator. The improved timing information could then be used to refine the circuit design process.